This invention is in the field of multi-port dynamic and static random access memories (DRAMs and SRAMs). Many current generation random access memories, particularly SRAMs, are being designed with multiple ports. Such devices have the advantage of providing access to the memory from several places in a system at the same time, making them much more flexible. This is advantageous in system design except when it causes contention problems because more than one port is attempting to write to the same memory address at the same time. In the case of such contention, one port may try to write one set of data into the address and another port a different set of data.
What is required is a graceful arbitration scheme so that the first port to attempt to write to the address is successful, and any subsequent port is forced to wait until the first port is finished writing. It is disastrous if both ports can write at the same time, which may cause the selected address to have some bits of its stored data sent by one port and other bits sent by another. This will cause an error. Furthermore, it is important that a second port attempting to read data while a first port is writing is either told to wait until the writing is complete, or is somehow signaled that the data it may be reading from that memory address is not the most up-to date data. Conflicts of this nature are called address contention.
Circuitry used to prevent such address contention is called arbitration circuitry. In the prior art, arbitration circuits, or arbiters, have used a comparator which compares the addresses selected by each port. When the arbiter detects a match, it then makes a decision as to which port asked for the selected address first.
After making that decision, the arbiter sends a busy signal to the second port seeking that address, indicating that the selected address is busy. Problems with these arbiters still arise if both ports select the same address at the same time. If the arbiter does not find matching addresses from more than one port, it needs to take no action. It only sends out a busy signal to the second port in the event of a match.
Recently introduced memory devices use address transition detection (ATD) circuitry to activate storage and retrieval of information. ATD substitutes for a clock to set up the memory for a read or a write operation. The memory learns that one or another port seeks to read from or write data into an address by sensing an address transition signal. An address transition signal is a change signal from the state where no access to an address is desired, to the state where access to that address is desired. It is the transition in state which signals to the memory that access to an address is sought.
ATD type memories have a problem using arbiter circuits of the prior art. If one port desires to write data into, or to read data out of a particular address, but the selected address is busy, after the arbiter receives the transition signal from the port seeking access, it sends a busy signal back to that port. When the busy condition terminates, of course, the second port is free to read or to write data into the formerly busy address of the memory. However, at that time, the second port is no longer transitioning from the non-seeking to the seeking state. Accordingly, it is no longer providing the required address transition signal indicating its desire to access the desired address. Therefore, in spite of the desired memory address now being free for access, the second port will not be capable of gaining access to it. To overcome this problem, memory circuits of the prior art require that the system design insures that when a port attempting to access an address was turned away because the address was busy, the system must first go to a different address and then come back to the formerly busy address. In that way, upon returning to the formerly busy address, the necessary transition signal will be regenerated, indicating a desire to access that address. Provided the address is then available, access will be permitted.
The problem with these system constraints required by the prior art memory circuits is the delay time encountered in going to a different address and coming back. This slows down average memory access time. If the user's program happens to generate a great deal of address contention (and many do), the part will be slowed considerably. Moreover, this system constraint of going away from a busy address and coming back makes the part incompatible with competitive parts which do not use address transition detection circuitry and thus do not place this constraint on the system.